Enhancing random-pattern coverage of programmable logic arrays via masking technique

Authors:
Hideo Fujiwara;Osamu Fujisawa;Kazunori Hikone
Affiliations:
Department of Electronics and Communications, Meiji University, Kawasaki, Japan;Department of Electronics and Communications, Meiji University, Kawasaki, Japan;Department of Electronics and Communications, Meiji University, Kawasaki, Japan
Venue:
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Year:
1988

Citing 4
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Abstract

This paper presents a testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns, The proposed design is realized with low area overhead by adding two mask arrays to the AND and OR arrays of the PLA. To clarify the effect of the masking technique, an experiment was performed in which 8 large PLAs were modified by adding various sizes of mask arrays and then fault simulation with random patterns for those modified and unmodijied PLAs was carried out to obtain ranabm-pattern test coverage curves. It was found that fault coverage could be significantly enhanced via the proposed masking technique with very low area overhead.