A New Built-In Self-Test Design for PLA's with Hligh Fault Coverage and Low Overhead
IEEE Transactions on Computers
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Enhancing random-pattern coverage of programmable logic arrays via masking technique
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitryresult in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existingscheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independentof the functions that the PLA realizes, and the 15-percent overhead includes the storage needed for the fault-free compressedoutput data. The fault coverage of this approach consists of all single and (1-2 -( 2n + m)) of all multiple stuck, crosspoint,and bridging faults in the original PLA and the additional test circuitry (n and m are the number of input variables and productterms, respectively). The article begins with a short review of existing design schemes.