A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers
Fault Detecting Test Sets for Reed-Muller Canonic Networks
IEEE Transactions on Computers
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers
An introduction to array logic
IBM Journal of Research and Development
A New Built-In Self-Test Design for PLA's with Hligh Fault Coverage and Low Overhead
IEEE Transactions on Computers
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
BIST-PLA: a built-in self-test design of large programmable logic arrays
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
Testable PLA design with minimal overheads
Integration, the VLSI Journal
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A BIST design of structured arrays with fault-tolerant layout
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A Testable PLA Design with Low Overhead and High Fault Coverage
IEEE Transactions on Computers
A New PLA Design for Universal Testability
IEEE Transactions on Computers
Higher certainty of error coverage by output data modification
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Lower overhead design for testability of programmable logic arrays
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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In this paper the problem of fault detection in easily testable programmable logic arrays (PLA's) is discussed. The easily testable PLA's will be designed by adding extra logic. These augmented PLA's have the following features: 1) for a PLA with n inputs and m columns (product terms), there exists a "universal" test set such that the test patterns and responses do not depend on the function of the PLA, but depend only on the size of the PLA (the values n and m); 2) the number of tests is of order n + m. For the augmented PLA's, universal test sets to detect faults in PLA's are presented. The types of faults considered here are single and multiple stuck faults and crosspoint faults in PLA's. Fault location and repair of PLA's are also considered.