Path Complexity of Logic Networks
IEEE Transactions on Computers
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results
IEEE Transactions on Computers
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
Instrumented architectural level emulation technology
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
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This paper surveys and summarizes the major contributions to the theory and practice of testable logic design. The first part, dealing with the theoretical procedures, discusses the design of easily testable combinational, sequential, and iterative networks, illustrating major techniques with common running examples. The second part comments on the more practical aspects such as board layout, test point siting, and other facilities for easing the problems associated with testing.