Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
DAC '78 Proceedings of the 15th Design Automation Conference
A New Approach to the Fault Location of Combinational Circuits
IEEE Transactions on Computers
Introduction to Special Section on Programmable Logic Arrays
IEEE Transactions on Computers
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
IEEE Transactions on Computers
Detection of Faults in Programmable Logic Arrays
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
A Design of Programmable Logic Arrays with Universal Tests
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
An introduction to array logic
IBM Journal of Research and Development
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
| Hi-index | 14.98 |
An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the algorithm is the determination of a fault set corresponding to the response obtained for a failed test. For the apparently small number of faults in this set, all other tests are generated and a fault table is formed. Subsequently, an adaptive procedure is used to diagnose the fault. Functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests. The large amount of computation time and storage required in the determination, a priori, of all the fault equivalence classes or in the construction of a fault dictionary are not needed here. A brief study of functional equivalence among the cross point faults is also made.