Diagnostic Techniques for the IBM S/390 600 MHz G5 Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Application of Information Theory to Sequential Fault Diagnosis
IEEE Transactions on Computers
Sequential Fault Diagnosis in Combinational Networks
IEEE Transactions on Computers
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays
IEEE Transactions on Computers
Algebraic Properties of Functions Affecting Optimum Fault-Tolerant Realizations
IEEE Transactions on Computers
Fault Diagnosis in Combinational Tree Networks
IEEE Transactions on Computers
Detection of Single, Stuck-Type Failures in Multivalued Combinational Networks
IEEE Transactions on Computers
Identification of Multiple Stuck-Type Faults in Combinational Networks
IEEE Transactions on Computers
S/390 G5 CMOS microprocessor diagnostics
IBM Journal of Research and Development
ATWIG, an automatic test pattern generator with inherent guidance
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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A systematic approach to the location of a single failure in a combinational logic network is presented. The method utilizes only the required tests and needs no fault table. The structure of the logic network is taken into consideration when selecting the tests to be applied. For tree networks, we start from the gate that generates a primary output and sequentially trace back through the stages of the network according to a fixed set of rules. At each stage we either locate the fault or determine the direction of the trace.