A method for generating weighted random test pattern
IBM Journal of Research and Development
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Failure Diagnosis of Structured VLSI
IEEE Design & Test
IC Failure Analysis: The Importance of Test and Diagnostics
IEEE Design & Test
Shmoo Plotting: The Black Art of IC Testing
IEEE Design & Test
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
An Efficient Scheme to Diagnose Scan Chains
Proceedings of the IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis and characterization of timing-related defects by time-dependent light emission
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Structured trace diagnosis for LSSD board testing—an alternative to full fault simulated diagnosis
DAC '81 Proceedings of the 18th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Deep Submicron Design Techniques for the 500MHz IBM S/390 G5 Custom Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
Diagnosis of scan path failures
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
A New Approach to the Fault Location of Combinational Circuits
IEEE Transactions on Computers
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
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This paper describes the strategies and techniques used to diagnose failures in the IBM 600-MHz S/390® G5 (Generation 5) CMOS microprocessor and the associated cache chips. The complexity, density, cycle time, and technology issues related to the hardware, coupled with time-to-market requirements, have necessitated a quick diagnostic turnaround time. Beginning with the first prototype of the G5 microprocessor chip, intense chip diagnostics and physical failure analysis (PFA) have successfully identified the root causes of many failures, including process, design, and random manufacturing defects. In this paper, three different diagnostic techniques are described that have enabled the G5 to achieve its objective. An example is presented for each technique to demonstrate its effectiveness.