Delay-optimal wiring plan for the microprocessor of high performance computing machines
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
IBM's S/390 G5 Microprocessor Design
IEEE Micro
Hybrid hierarchical timing closure methodology for a high performance and low power DSP
Proceedings of the 40th annual Design Automation Conference
System performance management for the S/390 parallel enterprise server G5
IBM Journal of Research and Development
Custom S/390 G5 and G6 microprocessors
IBM Journal of Research and Development
Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
IBM Journal of Research and Development
The S/390 G5 floating-point unit
IBM Journal of Research and Development
S/390 G5 CMOS microprocessor diagnostics
IBM Journal of Research and Development
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High frequency microprocessor designs require rigorous design guidelines, design methodology advancements, and novel approaches in circuit design style for processors operating in the high megahertz range. Timing closure becomes the single most important design issue, however, other design metrics such as area, power and noise need to be given equal consideration within the design cycle. Custom design techniques were used through out the logic circuits and arrays as well as the overall design planning for the 500 Mhz microprocessor cycle time.