Lower overhead design for testability of programmable logic arrays

Authors:
Saied Bozorgui-Nesbat;Edward J. McCluskey
Affiliations:
Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA;Center for Reliable Computing, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

A new technique for designing easily testable PLAs is presented. The salient features of this technique are: 1) low overhead, 2) high fault coverage, 3) simple design, 4) little or no impact on normal operation of PLA and 5) elimination of the need for test pattern generation. This technique consists of the addition of a small number of bit lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and dev ices tested. Using this technique all multiple stuck-at faults, as well as all multiple extra and multiple missing device faults, are detected.