DAC '78 Proceedings of the 15th Design Automation Conference
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
Lower Overhead Design for Testability of Programmable Logic Arrays
IEEE Transactions on Computers - The MIT Press scientific computation series
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Lower overhead design for testability of programmable logic arrays
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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This paper describes a heuristic method for generating test patterns for Programmable Logic Arrays (PLAs). Exploiting the regular structure of PLAs, both random and deterministic test-pattern generation techniques are combined to achieve coverage of crosspoint defects. Patterns to select or deselect product terms are generated through direct inspection of an array; test paths to an observable output are established by successive, rapidly converging assignmemnts of primary input values. Results obtained with a PL/I program implementation of the method are described; these results demonstrate that the method developed is both effective and computationally inexpensive.