A Testable PLA Design with Low Overhead and High Fault Coverage

Authors:
Javad Khakbaz
Affiliations:
Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305./ Memorex Corporatio
Venue:
IEEE Transactions on Computers
Year:
1984

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Abstract

A new design of testable PLA's is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA's. This design, however, is not appropriate for built-in test.