Higher certainty of error coverage by output data modification

Authors:
Y. Zorian;V. K. Agarwal
Affiliations:
Department of Electrical Engineering, McGill University, Montreal, Quebec;Department of Electrical Engineering, McGill University, Montreal, Quebec
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

With the increasing interest in Built-In-Testing, new approaches which can provide better error coverage than the conventional polynomial division (that is, multi-input LFSR) schemes are being developed. In this paper, a completely new approach is described which provides tremendous improvement in the error coverage with little additional silicon area on the Chip-Under-Test. The new scheme works with the scan concept, and is applicable to any general circuit.