A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
A defect-tolerant and fully testable PLA
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
BIST PLAs, pass or fail—a case study
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On Dictionary-Based Fault Location in Digital Logic Circuits
IEEE Transactions on Computers
On the generation of small dictionaries for fault location
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An Improved Analytical Yield Evaluation Method for Redundant RAM's
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
| Hi-index | 14.98 |
An approach to the design of reconfigurable programmable logic arrays (RPLAs) is proposed in which diagnosis of faults and reconfiguration are performed simultaneously. The approach also takes advantage of a laser programmable interconnect to simplify the test circuitry and area overhead. The RPLA design presented makes it possible to diagnose and repair faults on bit lines, product lines, and output lines. The unrepairable area in the RPLA is kept to a minimum. Only one extra input is required for testability. A mapping process for masking out missing crosspoint faults is employed to further enhance the yield of PLAs. Experimental results on the area overhead and the yield of the proposed RPLAs are presented. The field of the proposed RPLAs is higher than that of the original PLAs.