On the Design of High-Yield Reconfigurable PLA's
IEEE Transactions on Computers
Fault dictionary compression and equivalence class computation for sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Failure Diagnosis of Structured VLSI
IEEE Design & Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Coupling Electron-Beam Probing with Knowledge-Based Fault Localization
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A maximal resolution guided-probe testing algorithm
DAC '81 Proceedings of the 18th Design Automation Conference
Fault diagnosis based on effect-cause analysis: An introduction
DAC '80 Proceedings of the 17th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Dynamic fault diagnosis on reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The Effects of Test Compaction on Fault Diagnosis
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Compact Dictionaries for Fault Diagnosis in Scan-BIST
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
An Efficient Dictionary Organization for Maximum Diagnosis
Journal of Electronic Testing: Theory and Applications
A test pattern ordering algorithm for diagnosis with truncated fail data
Proceedings of the 43rd annual Design Automation Conference
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
Journal of Electronic Testing: Theory and Applications
Design and analysis of compact dictionaries for diagnosis in scan-BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved diagnosis using enhanced fault dominance
Integration, the VLSI Journal
| Hi-index | 14.98 |
In this work, fault location based on a fault dictionary is considered at the chip level. To justify the use of a precomputed dictionary in terms of computation time, the computational effort invested in computing a dictionary is first analyzed. The number of circuit diagnoses that need to be performed dynamically, without the use of precomputed knowledge, before the overall diagnosis effort exceeds the effort of computing a dictionary, is studied. Experimental results on ISCAS-85 circuits show that for relatively small numbers of diagnoses, a precomputed dictionary is more efficient than dynamic diagnosis. Next, a method to derive small dictionaries without losing resolution of modeled faults is proposed, based on extended pass/fail analysis. The same procedure is applicable for selecting internal observation points to increase the resolution of the test set. Methods to compact the resulting dictionary further, using compaction techniques generally applied to fault detection, are then described. Experimental results are presented to demonstrate the effectiveness of the proposed methods.