Fault diagnosis based on effect-cause analysis: An introduction
DAC '80 Proceedings of the 17th Design Automation Conference
Multi-defect real time diagnosis using a single pin probe
DAC '76 Proceedings of the 13th Design Automation Conference
An automated probing procedure for board testing
DAC '76 Proceedings of the 13th Design Automation Conference
On Dictionary-Based Fault Location in Digital Logic Circuits
IEEE Transactions on Computers
Dynamic fault diagnosis on reconfigurable hardware
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A simple technique for locating gate-level faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
ATS '95 Proceedings of the 4th Asian Test Symposium
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis
IEEE Transactions on Computers
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe
Computing observation vectors for max-fault min-cardinality diagnoses
AAAI'08 Proceedings of the 23rd national conference on Artificial intelligence - Volume 2
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The existing guided-probe testing procedures employ a simple strategy of following error path(s). This strategy may fail to locate faults (or may produce a wrong diagnostic) in the following situations: 1. Faults affecting lines connected to buses or wired-or junctions. 2. Faults whose error paths form closed asynchronous loops. 3. Faults which generate pseudo-intermittent symptoms. 4. Faults which do not propagate errors to the probed points. In this paper we introduce a new guided-probe algorithm which overcomes these difficulties. Our algorithm always achieves the maximal diagnostic resolution obtainable under the applied test.