Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Generation and application of pseudorandom sequences for random testing
Generation and application of pseudorandom sequences for random testing
Fault diagnosis of digital circuits
Fault diagnosis of digital circuits
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
On Dictionary-Based Fault Location in Digital Logic Circuits
IEEE Transactions on Computers
Improved fault diagnosis in scan-based BIST via superposition
Proceedings of the 37th Annual Design Automation Conference
Diagnosis for scan-based BIST: reaching deep into the signatures
Proceedings of the conference on Design, automation and test in Europe
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
Fault Diagnosis in Scan-Based BIST
Proceedings of the IEEE International Test Conference
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment
Proceedings of the conference on Design, automation and test in Europe
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Scan-based BIST fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Creating small fault dictionaries [logic circuit fault diagnosis]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a new technique for uniquely identifying a single failing vector in an interval of test vectors. This technique is applicable to combinational circuits and for scan-BIST in sequential circuits with multiple scan chains. The proposed method relies on the linearity properties of the MISR and on the use of two test sequences, which are both applied to the circuit under test. The second test sequence is derived from the first in a straightforward manner and the same test pattern source is used for both test sequences. If an interval contains only a single failing vector, the algebraic analysis is guaranteed to identify it. We also show analytically that if an interval contains two failing vectors, the probability that this case is interpreted as one failing vector is very low. We present experimental results for the ISCAS benchmark circuits to demonstrate the use of the proposed method for identifying failing test vectors.