BIST PLAs, pass or fail—a case study

Authors:
Shambhu J. Upadhyaya;John A. Thodiyil
Affiliations:
Department of Electrical and Computer Engineering, State University of New York at Buffalo, Buffalo, New York;Department of Electrical and Computer Engineering, State University of New York at Buffalo, Buffalo, New York
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

Citing 2
Cited 1

On the Design of High-Yield Reconfigurable PLA's

IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis

Experiments with autonomous test of PLAs

EURO-DAC '91 Proceedings of the conference on European design automation

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Abstract

Numerous Built-In Self Testing (BIST) designs now exist for the testing of Programmable Logic Arrays (PLA), but their practical usefulness has not been studied. In this paper, we implement and compare several BIST designs using a common methodology of implementation. We also perform an yield analysis to characterize the yield degradation due to the BIST design methodology. Our preliminary findings of this work is that BIST approach results in considerable degradation of yield, and therefore may not be suitable as a test vehicle for PLAs.