A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On the Evaluation of Arbitrary Defect Coverage of Test Sets
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
IEEE Transactions on Computers
Design for Testability A Survey
IEEE Transactions on Computers
Fault Diagnosis of MOS Combinational Networks
IEEE Transactions on Computers
On Combinational Networks with Restricted Fan-Out
IEEE Transactions on Computers
Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic
IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
Separating and Completely Separating Systems and Linear Codes
IEEE Transactions on Computers
On Closedness and Test Complexity of Logic Circuits
IEEE Transactions on Computers
Monotone Functions in Sequential Circuits
IEEE Transactions on Computers
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
An approach to the design of highly reliable and fail-safe digital systems
AFIPS '74 Proceedings of the May 6-10, 1974, national computer conference and exposition
Derivation of Minimal Test Sets for Monotonic Logic Circuits
IEEE Transactions on Computers
On the Complexity of Estimating the Size of a Test Set
IEEE Transactions on Computers
| Hi-index | 15.02 |
A derivation of test sets S0and S1for irredundant unate logical circuits is presented. It is shown that these sets (S0and S1, respectively) detect all stuck-at-0 and stuck-at-1 faults in all realizations with no internal inverters of a given unate function. They can be obtained easily from the minimum sum and minimum product forms, from a Karnaugh map, o