IEEE Transactions on Computers
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
Derivation of Minimum Test Sets for Unate Logical Circuits
IEEE Transactions on Computers
Easily Testable Realizations ror Logic Functions
IEEE Transactions on Computers
A Design Procedure for Fault-Locatable Switching Circuits
IEEE Transactions on Computers
Universal test sets for logic networks
SWAT '72 Proceedings of the 13th Annual Symposium on Switching and Automata Theory (swat 1972)
A New Approach to the Design of Testable PLA's
IEEE Transactions on Computers
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays
IEEE Transactions on Computers
Fault Diagnosis of MOS Combinational Networks
IEEE Transactions on Computers
Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic
IEEE Transactions on Computers
Efficient Design of Self-Checking Checker for any m-Out-of-n Code
IEEE Transactions on Computers
IEEE Transactions on Computers
PLA Implementation of k-out-of-n Code TSC Checker
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
A Module-Level Testing Approach for Combinational Networks
IEEE Transactions on Computers
On Closedness and Test Complexity of Logic Circuits
IEEE Transactions on Computers
A Practical Approach to Fault Detection in Combinational Networks
IEEE Transactions on Computers
Robust Coupling Delay Test Sets
Journal of Electronic Testing: Theory and Applications
| Hi-index | 15.01 |
The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid.