An Efficient Algorithm for Finding an Irredundant Set Cover
Journal of the ACM (JACM)
Logic Design of Digital Systems
Logic Design of Digital Systems
A Procedure for Selecting Diagnostic Tests
IEEE Transactions on Computers
Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
Fault-Tolerant Computing: An Introduction and a Perspective
IEEE Transactions on Computers
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
On Minimally Testable Logic Networks
IEEE Transactions on Computers
Structural Factors in the Fault Diagnosis of Combinational Networks
IEEE Transactions on Computers
Computer Diagnosis Using the Blocking Gate Approach
IEEE Transactions on Computers
Complete Test Sets for Logic Functions
IEEE Transactions on Computers
An Analysis Model for Digital System Diagnosis
IEEE Transactions on Computers
A method of diagnostic test generation
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
Iteratively Realized Sequential Circuits
IEEE Transactions on Computers
Improved Procedures for Determining Diagnostic Resolution
IEEE Transactions on Computers
Universal Test Sets for Logic Networks
IEEE Transactions on Computers
An integrated approach to automated computer maintenance
FOCS '65 Proceedings of the 6th Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1965)
Design for Testability A Survey
IEEE Transactions on Computers
Fault-Tolerant Computing: A Introduction
IEEE Transactions on Computers
A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits
IEEE Transactions on Computers
A Functional Approach to Testing Bit-Sliced Microprocessors
IEEE Transactions on Computers
Controllability and Fault Observability in Modular Combinational Circuits
IEEE Transactions on Computers
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A module-level testing approach for combinational networks which employs hardware modification and a simplified test generation procedure is described. The approach is based on a directed graph model for the network derived at the module level. The objectives of the approach are to deal with testing directly at the module level, to use cataloged tests for the modules in the network environment, and to generate a fault detection test set with "good" fault location capability. Networks which consist of single-output modules are treated initially and then the results are extended to networks which consist of multiple-output modules. Hardware modification and test generation procedures are illustrated.