Fault Testing and Diagnosis in Combinational Digital Circuits
IEEE Transactions on Computers
Analyzing Errors with the Boolean Difference
IEEE Transactions on Computers
IEEE Transactions on Computers
A structural theory of machine diagnosis
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
A Module-Level Testing Approach for Combinational Networks
IEEE Transactions on Computers
A method of test generation for fault location in combinational logic
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
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A variety of diagnostic techniques have been proposed and applied to error detection and location in computers. The efficiency of the tests generated by them varies from machine to machine depending on the scale of the system, its logic organiztion, and the employed hardware technology. The impact of highly integrated circuitry is changing the trend in logical design of computers.