A method of test generation for fault location in combinational logic

Authors:
Y. Koga;C. Chen;K. Naemura
Affiliations:
University of Illinois, Urbana, Illinois;University of Illinois, Urbana, Illinois;Nippon Telegraph and Telephone Public Corporation, Musashino, Tokyo, Japan
Venue:
AFIPS '70 (Fall) Proceedings of the November 17-19, 1970, fall joint computer conference
Year:
1970

Citing 3
Cited 1

Fault Testing and Diagnosis in Combinational Digital Circuits

IEEE Transactions on Computers
A structural theory of machine diagnosis

AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
A method of diagnostic test generation

AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference

System Modeling and Testing Procedures for Microdiagnostics

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

The Path Generating Method is a simple procedure to obtain, from a directed graph, an irredundant set of paths that is sufficient to detect and isolate all distinguishable failures. It was developed as a tool for diagnostic generation at the system level, e.g., to test data paths and register loading and to test a sequence of transfer instructions. But it has been found to be a powerful tool for test generation for combinational logic networks as well.