Universal Test Sets for Logic Networks

Authors:
Sheldon B. Akers
Affiliations:
Electronics Laboratory, General Electric Company, Syracuse, N.Y. 13201.
Venue:
IEEE Transactions on Computers
Year:
1973

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Abstract

This paper examines the problem of finding a single universal test set that will test any of a variety of different implementations of a given switching function. It is shown that, for AND/OR networks, universal test sets may be found that detect not only all single faults but all multiple faults as well. The minimality and size of these sets are examined and their derivation for incomplete functions is described.