A Design Procedure for Fault-Locatable Switching Circuits

  • Authors:

  • S. M. Reddy

  • Affiliations:

  • Department of Electrical Engineering, University of Iowa

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1972

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Abstract

A technique to design fault-locatable combinational switching circuits is given. The networks resulting from the application of the proposed technique have at most three levels of gates.