Derivation of Minimal Test Sets for Monotonic Logic Circuits

Authors:
Ramaswami Dandapani
Affiliations:
Department of Computer Science, The University of Iowa, Iowa City, Iowa 52240.
Venue:
IEEE Transactions on Computers
Year:
1973

Citing 2
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Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions

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Fault Diagnosis of MOS Combinational Networks

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Design of Fail-Safe Sequential Machines Using Separable Codes

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Efficient Design of Self-Checking Checker for any m-Out-of-n Code

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On Closedness and Test Complexity of Logic Circuits

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Abstract

It is shown that the number of maximal false vertices and minimal true vertices is the minimum number of tests required to detect all s-a-1 and s-a-0 faults in any irredundant two-level realization of a 2-monotonic function.