PLA based synthesis and testing of hazard free logic

Authors:
U. K. Bhattacharyya;I. Sen Gupta;S. Shyama Nath;P. Dutta
Affiliations:
-;-;-;-
Venue:
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Year:
1995

Citing 2
Cited 2

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Abstract

This paper presents a divide and conquer approach for the hazard-free realization of combinational networks. The circuit is partitioned into a set of supergates which are individually made hazard-free. Since each supergate has to be implemented in two-level form, the circuit can be implemented as a multilevel network of PLAs. A modified supergate partitioning for multi-output circuits has also been proposed. Experiments to evaluate the testability of the synthesized circuits have been carried out.