A parallel PLA minimization program

Authors:
R. Galivanche;S. M. Reddy
Affiliations:
1300 N. Alma School Road, Motorola Inc., Chandler, Arizona;Dept. of Elect. and Comp. Eng., University of Iowa, Iowa City, Iowa
Venue:
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Year:
1987

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Abstract

In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The parallel algorithm was implemented on a shared memory multicomputer system. In the course of development of the parallel algorithm, some changes were made to ESPRESSO-MV which resulted in lower computing time. Experimental results using 105 PLAs are included.