Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool

Authors:
Robert N. Mayo;John K. Ousterhout
Affiliations:
Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Computer Science Division, Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Venue:
DAC '83 Proceedings of the 20th Design Automation Conference
Year:
1983

Citing 3
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Abstract

Tile packing is a technique for VLSI module generation that uses both graphical and procedural information. A graphical editor is used to specify tiles of mask information, then procedures are written to arrange the tiles into modules. This technique combines the visual power of graphical systems with the programming power of procedural systems. Since all of the mask information is contained in the tiles, the same procedures may be used for different design rules or technologies, merely by supplying a different set of tiles. We describe the procedural and graphical interfaces, and discuss two module generators that have been built with them.