The layout synthesizer: an automatic Netlist-to-Layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
SOLO: a generator of efficient layouts from optimized MOS circuit schematics
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Algorithms and Techniques for VLSI Layout and Synthesis
Algorithms and Techniques for VLSI Layout and Synthesis
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
Optimal Chaining of CMOS Transistors in a Functional Cell
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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Synthesis has been used to generate layouts for MOS circuits having a wide range of complexity, from a few to thousands of transistors. Until recently, automatic layout was confined to cell based approaches using a library of pre-laid out cells, such as standard cells or sea-of-gates primitives. The direct use of arbitrary cells, or the quick generation of new library items, is now receiving increased attention. This paper presents an overview of the main issues specific to the cell generation of MOS digital circuits.