Linear algorithms for two CMOS layout problems
Proc. of the Aegean workshop on computing on VLSI algorithms and architectures
Layout optimization of CMOS functional cells
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Dual Eulerian Properties of Plane Multigraphs
SIAM Journal on Discrete Mathematics
The recognition of double Euler trails in series-parallel networks
Journal of Algorithms
Graph Drawing: Algorithms for the Visualization of Graphs
Graph Drawing: Algorithms for the Visualization of Graphs
Finding Double Euler Trails of Planar Graphs in Linear Time
FOCS '99 Proceedings of the 40th Annual Symposium on Foundations of Computer Science
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Given a series-parallel graph, we consider the problem of drawing its layout in the plane (and the planar dual of the layout) such that the euler count of the layout is minimized. This problem is of considerable importance to the design of CMOS circuits. Even though it was believed that there cannot exist a polynomial time algorithm for this problem, we have been able to design a polynomial time algorithm. The degree of the polynomial is unrealistically large. The main interest is in the existence of a polynomial time algorithm for the problem. We are not aware of any natural problem for which a natural dynamic programming based algorithm has such a large degree.