Power and delay macro-modeling for submicronic CMOS process: application to low power design
Proceedings of the first session on Low-power, low-voltage integrated circuits : technology and design: technology and design
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
ISPD '99 Proceedings of the 1999 international symposium on Physical design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Platform-Based Design: A Path to Efficient Design Re-Use
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
An industrial view of electronic design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Standard cell libraries have been successfully used for years, however with the emergence of new technologies and the increasing complexity of designs, this concept becomes less and less attractive. Most of the time, cells are too generic and not well suited to the block being created. As a result the final design is not well optimized in terms of timing, power and area.This paper describes a new approach based on transistor level layout synthesis for CMOS IP cores rapid prototyping (~100k transistors).