Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

  • Authors:
  • Michael A. Riepe;Karem A. Sakallah

  • Affiliations:
  • University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI

  • Venue:
  • ISPD '99 Proceedings of the 1999 international symposium on Physical design
  • Year:
  • 1999

Quantified Score

Hi-index 0.00

Visualization

Abstract