Synthesis of combinational logic using three-input majority gates
FOCS '62 Proceedings of the 3rd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1962)
Semi-modular Latch Chains for Asynchronous Circuit Design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Synthesis Algorithms for 2-level MOS Networks
IEEE Transactions on Computers
Power Minimization Problems of Logic Networks
IEEE Transactions on Computers
Partition of Boolean Functions ror Realization with Multithreshold Threshold Logic Elements
IEEE Transactions on Computers
Fault Diagnosis of MOS Combinational Networks
IEEE Transactions on Computers
Synthesis of Diagnosable FET Networks
IEEE Transactions on Computers
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
Synthesis of Multilevel Feed-Forward MOS Networks
IEEE Transactions on Computers
Gate-Interconnection Minimization of Switching Networks Using Negative Gates
IEEE Transactions on Computers
Synthesis of Feed-Forward MOS Networks with Cells of Similar Complexities
IEEE Transactions on Computers
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results
IEEE Transactions on Computers
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In this paper we develop an algorithm to design a switching network using only gates which represent negative functions. The number of gates in the network is minimized under the conditions that 1) the network consists of two levels, and 2) no fan-in restriction on each gate is imposed.