Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs

Authors:
Chingwei Yeh;Min-Cheng Chang;Yin-Shuin Kang
Affiliations:
-;-;-
Venue:
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Year:
1999

Citing 5
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Abstract

One recent approach for power reduction is to employ different supply voltages for different parts of a design. This paper presents optimization methods that promote the use of dual supply voltages for power-driven designs. We first propose an iterative gate sizing and voltage scaling paradigm that progressively scales down the supply voltage under fixed timing constraint. Then, we propose a new physical layout style that supports dual supply voltages for cell-based designs. The new layout style can be automatically generated via a simulated annealing based placement algorithm. Experimental results using the MCNC benchmark circuits show that the proposed techniques produce very encouraging results.