Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
Efficient transistor-level design of CMOS gates
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of different methods. We describe which figures of merit, including the logical effort, affect the design quality of cell transistor networks. Further, we compare six different approaches that generate transistor networks, including two with guaranteed theoretical minimum length transistor chains. This comparison shows that minimum length chains reduce the logical effort of the networks.