Worst and Best Irredundant Sum-of-Products Expressions
IEEE Transactions on Computers
Design and synthesis of dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A comparative study of CMOS gates with minimum transistor stacks
Proceedings of the 20th annual conference on Integrated circuits and systems design
Accurate Total Static Leakage Current Estimation in Transistor Stacks
AICCSA '06 Proceedings of the IEEE International Conference on Computer Systems and Applications
A methodology for transistor-efficient supergate design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An improvement on the complexity of factoring read-once Boolean functions
Discrete Applied Mathematics
Switch level optimization of digital CMOS gate networks
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Efficient method to compute minimum decision chains of Boolean functions
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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The transistor arrangement optimization is an effective possibility to improve VLSI design, especially when generating CMOS logic gates to be inserted in standard cell libraries. This paper addresses this issue and presents a new methodology to generate efficient transistor networks. Starting from an input ISOP, the proposed method is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. By applying the proposed approach, it is possible to achieve optimized transistor arrangements since greedy choices are avoided during part of the generation process. The performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.