Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
IEEE Transactions on Circuits and Systems II: Express Briefs
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.03 |
We present single- and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay, and power in an experimental 0.1- and 0.13-μm CMOS technologies as well as a 0.13-μm floating-body partially depleted silicon-on-insulator (PDSOI) process. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/static logic gates using binary decision diagrams (BDDs). The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that both single- and dual-rail mixed PTL circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay and power in bulk CMOS as well as silicon-on-insulator (SOI) CMOS technologies. The average power of single- and dual-rail mixed PTL/Static ISCAS'85 benchmark circuits using the proposed method in the 0.1-μm bulk CMOS process are 73% and 50% better than their static counterparts with performance gains of 5% and 10%, respectively.