Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Logic synthesis for vlsi design
Logic synthesis for vlsi design
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In this paper, single-rail and dual-rail mixed pass-transistorlogic (PTL) and static CMOS circuits are presented.The circuits were synthesized using a genetic algorithmthat determines the best mixture of PTL and static cellsbased on area and power. The mixed PTL/Static circuits usingthe proposed method are compared with their static counterpartssynthesized using a commercial logic synthesis toolin terms of area, delay and power in a 0.13µm floating-body partailly depleted silicon-on-insulator (SOI) and a 0.13µmbulk CMOS technologies. Our experimental results on benchmarkcircuits from a commercial microprocessor indicatesthat the proposed mixed PTL/Static circuits in both SOI andbulk CMOS technology outperforms their static counterpartsin power consumption and/or performance.