Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
A fast and accurate technique to optimize characterization tables for logic synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Rapid and accurate latch characterization via direct Newton solution of setup/hold times
Proceedings of the conference on Design, automation and test in Europe
An Efficient Method for Fast Delay and SI Calculation Using Current Source Models
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nonlinear driver models for timing and noise analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fortifying analog models with equivalence checking and coverage analysis
Proceedings of the 47th Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient compression and handling of current source model library waveforms
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
The Liberty Format is an open source industry standard for library modeling that has seen significant enhancement in recent years to address the challenges introduced by the new smaller technologies at 65nm and below. Issues associated with modeling Timing, Power and Noise have seen an explosion in complexity. The paper discusses the challenges introduced by the new high accuracy models and techniques to ameliorate them for Library providers.