A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Addressing library creation challenges from recent Liberty extensions
Proceedings of the 45th annual Design Automation Conference
Receiver modeling for static functional crosstalk analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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This paper presents a novel and flexible modeling technique to generate accurate linear and nonlinear driver models with applications in timing and noise analysis. The new technique, based on Galerkin's finite elements method, is very efficient because it relies on existing logic block characterization for timing, does not require additional nonlinear circuit simulations during modeling, and generates reusable models. The performance of the proposed modeling technique is exemplified in two different implementations: nonlinear driver models for delay noise analysis and piece-wise linear driver models for static-timing analysis.