Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Efficient AC and noise analysis of two-tone RF circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Numerical Initial Value Problems in Ordinary Differential Equations
Numerical Initial Value Problems in Ordinary Differential Equations
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 44th annual Design Automation Conference
NBTI-aware flip-flop characterization and design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Addressing library creation challenges from recent Liberty extensions
Proceedings of the 45th annual Design Automation Conference
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Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(τ) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS latch/register structures, obtaining speedups of 4-10 × over the current standard of binary search.