Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Proceedings of the 43rd annual Design Automation Conference
Rapid and accurate latch characterization via direct Newton solution of setup/hold times
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
The impact of NBTI on the performance of combinational and sequential circuits
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guest Editorial: Current Trends in Low-Power Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Aging-resilient design of pipelined architectures using novel detection and correction circuits
Proceedings of the Conference on Design, Automation and Test in Europe
NBTI-aware power gating design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, different types of flip-flops exhibit different levels of susceptibility to NBTI-induced change in their setup/hold time values. Finally, an NBTI-aware transistor sizing technique can minimize the NBTI effect on timing characteristics of the flip-flops.