NBTI-aware flip-flop characterization and design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Statistical timing analysis of flip-flops considering codependent setup and hold times
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops
Proceedings of the 13th international symposium on Low power electronics and design
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Methodology to achieve higher tolerance to delay variations in synchronous circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing modeling of flipflops considering aging effects
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Iterative timing analysis considering interdependency of setup and hold times
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits
Microelectronics Journal
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A methodology is proposed to exploit the interdependence between setup- and hold-time constraints in static timing analysis (STA). The methodology consists of two phases. The first phase includes the interdependent characterization of sequential cells, resulting in multiple constraint pairs. The second phase includes an efficient algorithm that exploits these multiple pairs in STA. The methodology improves accuracy by removing optimism and reducing unnecessary pessimism. Furthermore, the tradeoff between setup and hold times is exploited to significantly reduce timing violations in STA. These benefits are validated using industrial circuits and tools, exhibiting up to 53% reduction in the number of constraint violations as well as up to 48% reduction in the worst negative slack, which corresponds to a 15% decrease in the clock period