Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An analytical model for negative bias temperature instability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 44th annual Design Automation Conference
Exploiting Setup–Hold-Time Interdependence in Static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Traditionally, the timing of a flipflop is modeled by a single constraint pair of setup and hold times. For timing verification of digital circuits both timing constraints should not be violated. Furthermore, the interdependency of these two quantities is exploited and multiple constraint pairs are taken as valid setup and hold times. STA Tools can be easily constructed by the propagation of arrival times. In this paper, we present a comprehensive study of flipflop timing behavior and extend the timing modeling by explicitly building the functional relationship between clock-to-q delay and timing parameters at flipflop data input in order to break the timing boundaries and thus allow interdependency of different computation stages to be analyzed at gate level. Aging effects HCI and NBTI are also considered in the modeling to pave the way for aging analysis.