The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Operations research: principles and practice, 2nd ed.
Operations research: principles and practice, 2nd ed.
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
ATV: an abstract timing verifier
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synchronous path analysis in MOS circuit simulator
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification on a 1.2M-device full-custom CMOS design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On the temporal equivalence of sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automated multi-cycle symbolic timing verification of microprocessor-based designs
DAC '94 Proceedings of the 31st annual Design Automation Conference
On testing wave pipelined circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
The practical application of retiming to the design of high-performance systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
Optimal design of synchronous circuits using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Specification of timing constraints for controller synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Clock schedule verification under process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing model extraction for sequential circuits considering process variations
Proceedings of the 2009 International Conference on Computer-Aided Design
Integration, the VLSI Journal
Statistical time borrowing for pulsed-latch circuit designs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Timing modeling of flipflops considering aging effects
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Iterative timing analysis considering interdependency of setup and hold times
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods
Proceedings of the International Conference on Computer-Aided Design
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We present a succinct formulation of the timing constraints for latch-controlled synchronous digital circuits. We show that the constraints are mildly nonlinear, and prove the equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem. We present an LP-based algorithm which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multi-phase overlapped clocks. We illustrate the formulation and an initial implementation of the algorithm on some example circuits.