Methodology to achieve higher tolerance to delay variations in synchronous circuits
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing modeling of flipflops considering aging effects
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Iterative timing analysis considering interdependency of setup and hold times
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits
Microelectronics Journal
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Characterizing setup/hold times of latches and registers, which is a task crucial for achieving timing closure of large digital designs, typically occupies months of computation in semiconductor industries. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation ; this nonlinear algebraic formulation is derived from, and embeds within it, the state-transition function of the latch. We first present a technique to characterize setup and hold times independently of each other: by decoupling into two equations and and solving each equation using the Newton-Raphson method. Next, we also present a method for interdependent characterization of latch setup/hold times - a core component of techniques for pessimism reduction in timing analysis. We achieve this by solving the underdetermined nonlinear equation using a Moore-Penrose pseudoinverse-based Newton method. Furthermore, we use null-space information from the Newton's Jacobian matrix to efficiently find constant-clock-to- contours (in the setup/hold time plane) via an Euler-Newton curve-tracing procedure. We validate fast convergence and computational advantage for independent characterization on transmission gate and latch/register structures, obtaining speedups of , at high levels of accuracy, over the current standard of binary search. We validate the method for interdependent characterization on true single-phased clock and , obtaining speedups of more than 10 for tracing 17-24 points, over prior approaches while achieving superior accuracy; this speedup linearly increases with the precision with which curve tracing is desired. We also apply our method for interdependent characterization on a transmission gate register to illustrate limitations of our method.