A fast and accurate technique to optimize characterization tables for logic synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Transistor-level timing analysis using embedded simulation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Statistical waveform and current source based standard cell models for accurate timing analysis
Proceedings of the 45th annual Design Automation Conference
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
RDE-based transistor-level gate simulation for statistical static timing analysis
Proceedings of the 47th Design Automation Conference
Hi-index | 0.00 |
To increase the accuracy of static timing analysis, the traditional nonlinear delay models (NLDMs) are increasingly replaced by the more physical current source models (CSMs). However, the extension of CSMs into statistical models for statistical timing analysis is not easy. In this paper, we propose a novel correlation-preserving statistical timing analysis method based on transistor-level gate models. The correlations among signals and between process variations are fully accounted for. The accuracy and efficiency are obtained from statistical transistor-level gate models, evaluated using a smart Random Differential Equation (RDE)-based solver. The variational waveforms are available, allowing signal integrity checks and circuit optimization. The proposed algorithm is verified with standard cells, simple digital circuits and ISCAS benchmark circuits in a 45nm technology. The results demonstrate the high accuracy and speed of our algorithm.