An Upper Bound on Expected Clock Skew in Synchronous Systems
IEEE Transactions on Computers
Fast and accurate wire delay estimation for physical synthesis of large ASICs
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Coping with buffer delay change due to power and ground noise
Proceedings of the 39th annual Design Automation Conference
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
Contango: integrated optimization of SoC clock networks
Proceedings of the Conference on Design, Automation and Test in Europe
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
On construction low power and robust clock tree via slew budgeting
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Local merges for effective redundancy in clock networks
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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The International Symposium on Physical Design (ISPD) 2010 contest presents the challenge of synthesizing clock distribution networks that are tolerant to severe power-supply and wire-width variations. In particular, a robust clock network should satisfy the local clock skew (LCS) constraint, i.e., the clock skew between any pair of sequential elements that are closer than a user-specified distance is below a user-specified limit, even in the presence of variations. In this paper, we identify a few factors that help in tolerating these variations in clock trees. Our proposed clock tree router uses a two-stage flow to construct low-power clock trees for which the LCS constraints are met. Our clock tree router has been tested on ISPD'10 contest benchmark circuits. Extensive Monte-Carlo simulations showed that low power clock tree solutions could effectively handle variations, even when we imposed more stringent conditions in the experimental setup.