Timing analysis considering spatial power/ground level variation

Authors:
M. Hashimoto;J. Yamaguchi;H. Onodera
Affiliations:
Dept. Commun. & Comput. Eng., Kyoto Univ., Japan;Dept. Commun. & Comput. Eng., Kyoto Univ., Japan;Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

Citing 6
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Abstract

Spatial power/ground level variation causes power/ground level mismatch between driver and receiver, and the mismatch affects gate propagation delay. This work proposes a timing analysis method based on a concept called "PG level equalization" which is compatible with conventional STA frameworks. We equalize the power/ground levels of driver and receiver. The charging/discharging current variation due to equalization is compensated by replacing output load. We present an implementation method of the proposed concept, and demonstrate that the proposed method works well for multiple-input gates and RC load models.