Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A stochastic approach To power grid analysis
Proceedings of the 41st annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Worst-case circuit delay taking into account power supply variations
Proceedings of the 41st annual Design Automation Conference
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis considering spatial power/ground level variation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis considering temporal supply voltage fluctuation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Stochastic variational analysis of large power grids considering intra-die correlations
Proceedings of the 43rd annual Design Automation Conference
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical static timing analysis considering leakage variability in power gated designs
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power supply noise is becoming more and more influential on timing, though noise aware timing analysis has not been well established yet, because of several difficulties such as its dependency on input vectors and dynamic behavior. This paper proposes a static timing analysis considering power supply noise in which the dependency of noise on input vectors and spatial and temporal correlations are handled in a statistical manner. We construct a statistical model of power supply voltage that dynamically varies with spatial and temporal correlation, and represent it as a set of uncorrelated variables. We demonstrate that power voltage variation is highly correlated and adopting principal component analysis as an orthogonalization technique is effective in variable reduction. Experiments confirm the validity of our model and the accuracy of timing analysis. We also discuss the accuracy and CPU time in association with variable reduction